Last October, when Intel officially launched the 9th generation Core series processors, the company also used the opportunity to announce a partially new workstation processor, the Xeon W-3175X. Technically speaking, the architecture of the Xeon W-3175X is not new at the center – the sheer 28-core / 56-thread processor is based on Skylake-SP, just like the first wave of Xeon Scalable processors released in 2017 However, what Intel has done with The Xeon W-3175X is a selectivity that allows you to dismantle and adjust power and turbo boost profiles to increase frequency and ultimately performance compared to previous Skylake-SP parts. The Xeon W-3175X is also unlocked to allow for easier unlocking, such as multiple variables "K" skins.
To help sell this extremely powerful processor, Intel also attracted a couple of partner help to produce motherboards that could deliver high power when users want to switch Xeon W-3175X. On the ASUS ROG Dominus Extreme motherboard, we tested the Xeon W-3175X with, for example, 32 power phases and a dual 24-pin ATX, quad 8-pin EPS12V and two 6-pin 12V power supply to keep everything out of the processor. , on memory and PCI Express slots powered by high power when pressed much further than stocks.
Here's a quick breakdown of the core features and specifications of Intel Xeon W-3175X. Look at speed and feeds, and then we'll examine the hardware more closely and see how it works compared to many of today's top-end processors.
The Intel Xeon W-3175X is an Xeon W series with higher clocks and unlocked multipliers. Thanks to Intel HyperThreading (SMT) technology, the processor has 28 physical cores with 56 thread support. The W-3175X base clock is 3.1 GHz and its single core Turbo frequency is 4.3 GHz. For comparison, the Xeon Platinum 8180 28-core processor based on the same architecture has a base clock of 2.5 GHz and a max Turbo frequency of 3.8 GHz.
As already mentioned, the Xeon W-3175X is based on Skylake-SP, similar to Skylake-X and the original Skylake microarchitectures. Since we have included Skylake in all its forms in the past, we are not going to fall too deep here. However, if you want more background, we have some suggestions. In our original Intel Xeon Scalable series processor range, we discuss the complexity of Skylake-SP and Skylake-X, which is described in detail in our Core i7-7900X. Our Intel Skylake architecture preview from IDF is also worthwhile.
Intel Xeon W-3175X, Top and Bottom
However, there are some things about Skylake-SP, but we have to repeat. Like the Xeon Scalable Series, the Xeon W-3175X is manufactured using the Intel 14nm process. With this in mind, packing 28 cores in one monolithic form and pressing frequencies and uplifting will cause some high power requirements. The Xeon W-3175X is a 255W TDP, but when you see it a bit later, power consumption can be significantly higher when overclocking is activated.
The processor supports 6 memory channels (with standard RAS and ECC support), has 38.5 MB Intel Smart Cache, 48 integrated PCI Express 3.0 bands (additional 20 comes from C621 chipset) and requires a LGA3647 socket.
Skylake-SP quadruples the size of the L2 cache compared to older architectures, increasing it to 1 MB for one code, while the overall size of the L3 cache is reduced. Overall, however, there is still roughly the same cache size – the balance has just changed. Not only has the cache size changed, but also how it is used.
Intel has previously used an inclusive cache structure. However, with such a large L2 cache, Skylake-SP, an inclusive cache was no longer meaningful, as copies of cache data should be retained in multiple layers, effectively reducing the total amount of L3 available. And many of the L2 copies in the smallest L3 volume didn't make any sense. In order to increase the size of L2 and at the same time maintain the size of the L3 cache, Intel would have had to sacrifice the main number to keep the dying size in check, so it was decided to move to a non-inclusive cache structure. These changes result in a better rate of results in the largest, lower latency L2 cache and a slightly lower hit rate for the smaller L3.
Intel Skylake-SP Mesh Architecture
Linking all kernels, caches, and I / O Skylake-SP is an eye architecture that differs from the ring connection used in previous generators. However, the network, together with changes in the cache hierarchy, changes the overall performance profile of Skylake-SP (and Skylake-X) compared to other architectures. With increased kernel size and memory and I / O bandwidth, it became increasingly difficult to increase efficiency with a ring connection. A ring connection should require that data be sent over long rings (relatively speaking) to achieve, for example, the intended purpose. The new eye architecture addresses this constraint by interconnecting the elements of the chip in a wider way to ultimately increase the number of roads and improve efficiency.
Intel Xeon W-3175X CPU-Z Information
Return to the Intel Xeon W-3175X, see its CPU-Z components at idle, but under load and with just one kernel. Processor full turbo gain hit 3.8GHz with 1.04v. One kernel amplifier marked the 4.3GHz signal but was difficult to detect due to constant frequency fluctuations. The 4.1GHz to 4.2GHz watches were about 1.1V more common. Here is also a cache distribution. As you can see, the processor has a 64K (32K + 32K) L1 kernel, 1MB L2 to the kernel, and a total of 38.5 MB of shared L3.